1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device that includes a multiplexer which outputs internal data signals in synchronization with a plurality of internal clock signals having different phases.
2. Description of Related Art
Semiconductor devices that input and output data in synchronization with a clock signal, such as a synchronous dynamic random access memory (SDRAM), need a synchronizing circuit that synchronizes internal data signals with the clock signal. As described in Japanese Patent Application Laid-Open No. 2001-110185, a clocked gate circuit is used as the synchronizing circuit. In the semiconductor device described in Japanese Patent Application Laid-Open No. 2001-110185, internal data signals have the same amplitude as that of an internal power supply voltage which is lower than an external power supply voltage. A level shift circuit is therefore inserted into the signal paths of the internal data signals. Since the level shift circuit is inserted in a position immediately before the clocked gate circuit, the clocked gate circuit operates on the external power supply voltage as its power source.
If the external power supply voltage is used as the operating power source of the clocked gate circuit as in the semiconductor device described in Japanese Patent Application Laid-Open No. 2001-110185, there is little possibility that noise occurring from the operation of the clocked gate circuit will propagate to internal circuits.
In some semiconductor devices such as a DDR (Double Data Rate) SDRAM, data is output in synchronization with both edges (rising edge and falling edge) of a clock signal. Such type of semiconductor devices need a multiplexer having clocked gate circuits connected in parallel, and a clock dividing circuit for generating complementary internal clock signals. With such a configuration, there has been a possibility of interaction among noises and a drop in signal quality if the multiplexer and the clock dividing circuit are operated with the same internal power supply voltage.